1. Field of the Invention
The present invention relates to a reading circuit, a reference circuit, and a semiconductor memory device including such a reading circuit and such a reference circuit.
2. Description of the Related Art
In general, a reading circuit for reading data from a memory cell array including a plurality of memory cells supplies an electric current to a memory cell having data stored therein, and compares the current (cell current) flowing through the memory cell with a reference current so as to determine whether the level of the cell current is higher or lower than the level of the reference current. Thus, the data written in the memory cell is read. Such a system of reading data is referred to as a “current sensing system”.
For example, data is read from so-called two-level memory cells which can store 1-bit data in one memory cell as described below with reference to FIG. 9B. A first state in which the level of the cell current is higher than that of the reference current (corresponding to data “1”), and a second state in which the level of the cell current is lower than that of the reference current (corresponding to data “0”), are preset. The reference current level is set to an intermediate level between the first state and the second state. Then, the cell current level in the memory cell is compared with the reference current level, and thus the 1-bit data stored in the memory cell can be read. In actuality, the cell current and the reference current are subjected to current-voltage conversion, and the potential of a sensing line through which the cell current flows is compared with the potential of a reference line through which the reference current flows.
In addition to such two-level memory cells, multi-level memory cells have recently been studied which can store data of 2-bits or more in one memory cell, in order to increase the storage capacity and/or reduce the production cost of semiconductor chips.
In this specification, the term “multi-level memory cells” means tertiary or higher memory cells, i.e., memory cells which can store 1.5-bit data or more in one memory cell.
For example, data is read from quaternary memory cells which can store 2-bit data in one memory cell as described below with reference to FIG. 9A. Four states which the cell current can be in are preset. More specifically, a first state, a second state, a third state, and a fourth state are set in order of the cell current level. The cell current level is highest in the first state and lowest in the fourth state. In this example, the first state corresponds to data “11”, the second state corresponds to data “10”, the third state corresponds to data “01”, and the fourth state corresponds to data “00”.
Then, three reference current levels are set so as to be between the four states of the cell current. More specifically, a first reference current level L is set at an intermediate level between the first state (corresponding to data “11”) and the second state (corresponding to data “10”), a second reference current level M is set at an intermediate level between the second state (corresponding to data “10”) and the third state (corresponding to data “01”), and a third reference current level H is set at an intermediate level between the third state (corresponding to data “01”) and the fourth state (corresponding to data “00”).
The reference current levels set in this manner are compared with the cell current level in the memory cell, and thus the 2-bit data can be read in accordance with the cell current level.
In order to read from general multi-level memory cells which can store n-bit data in one memory cell, it is necessary to preset 2n states which the cell current can be in and also set 2n−1 reference current levels.
As can be appreciated from FIGS. 9A and 9B, in general, it is physically more difficult for a multi-level memory cell than a two-level memory cell to obtain a sufficient current level difference between the cell current levels and the reference current levels. In such a case where the current level difference between the cell current levels and the reference current levels is relatively small, it is not easy to obtain a sufficiently large operation margin, especially in a reading circuit.
In a multi-level memory cell, it is necessary to compare the cell current level with many types of reference current levels in order to read data stored in a memory cell. For example, in order to read 2-bit data, the cell current level in the memory cell needs to be compared with three reference current levels. This undesirably extends the read time.
In order to solve these problems, a plurality of systems have been proposed for reading data from a multi-level memory cell. One such system is a time division sensing system, by which the cell current level in the memory cell is compared with one reference current level at a time, and in accordance with the comparison result, the cell current level is compared with another reference current level. Thus, the current levels are compared sequentially in a time division manner. Another system is a parallel sensing system, by which the cell current level is compared with a plurality of reference current levels at a time.
As an example of the time division sensing system, an operation of reading data from multi-level memory cells which can store 2-bit data in one memory cell (FIG. 9A) will be described with reference to FIG. 10.
FIG. 10 is a circuit diagram of a conventional reading circuit J100 for reading data from memory cells in the time division sensing system.
In FIG. 10, the reading circuit J100 reads data from only one memory cell. This is merely exemplary, and the reading circuit J100 may read data from one selected memory cell among a plurality of memory cells.
The reading circuit J100 includes a current load circuit J1 for applying a voltage to a drain of a selected cell J7 from which data is to be read, so as to obtain a reading current (cell current), and a current load circuit J2 for obtaining a reference current.
A sensing line J9 is provided for connecting the drain of the selected cell J7 to the current load circuit J1, and a reference line J10 is provided for connecting the current load circuit J2 to a selection circuit J6. The selection circuit J6 connects one of resources J80 through J82 of the reference current to the current load circuit J2.
The sensing line J9 and the reference line J10 are respectively connected to input sections of a sense amplifier J3. The sense amplifier J3 senses the potential difference between the potential of the sensing line J9 and the potential of the reference line J10 and amplifies the potential difference.
An output section of the sense amplifier J3 is connected to a first data latch circuit J4 for latching an output from the sense amplifier J3 during a first sensing period and to a second data latch circuit J5 for latching an output from the sense amplifier J3 during a second sensing period, which is after the first sensing period.
The first data latch circuit J4 is connected to the selection circuit J6 via a line J111. The selection circuit J6 selects one of the resources J80 through J82 of the reference current in accordance with the output from the first data latch circuit J4, and connects the selected resource to the reference line J10.
The reading circuit J100 of the time division sensing system having the above-described structure reads data from the selected cell J7 in the following manner. In the following description, the selection circuit J6 connects the reference line J10 to the resource J80 in an initial state.
First, an appropriate voltage is applied to a gate and a drain of the selected cell J7, thereby generating a cell current flowing through the selected cell J7. Next, the potential of the sensing line J9 is dropped in accordance with the generated cell current.
Similarly, a reference current is generated flowing from the resource J80 selected by the selection circuit J6. In accordance with the reference current, the potential of the reference line J10 is dropped.
Then, the potential difference between the potential of the sensing line J9 and the potential of the reference line J10 is sensed and amplified by the sense amplifier J3. When the level of the cell current is lower than the level of the reference current, the sense amplifier J3 outputs “0”. When the level of the cell current is higher than the level of the reference current, the sense amplifier J3 outputs “1”.
The output from the sense amplifier J3 in the first sensing period is latched by the first data latch circuit J4.
The resource J80 of the reference current selected by the selection circuit J6 during the first sensing period is for obtaining a reference current level “M” which is between the second state (FIG. 9A) (corresponding to data “10”) and the third state (corresponding to data “01”) among the three reference current levels.
In general, as the resources J80 through J82, reference cells having the same structure and the same characteristics as those of the memory cell, whose threshold voltages are tightly adjusted, are used in order to obtain appropriate reference currents.
Next, based on the output from the sense amplifier J3 during the first sensing period, the output being latched by the first data latch circuit J4, the selection circuit J6 switches the resource of the reference current from J80 to J81 or J82.
When the first data latch circuit J4 latches data “0” (i.e., when the cell current level is lower than the reference current level), the resource of the reference current is switched to J81. When the first data latch circuit J4 latches data “1” (i.e., when the cell current level is higher than the reference current level), the resource of the reference current is switched to J82.
The resource J81 is for obtaining a reference current level “H” which is between the third state (FIG. 9A) (corresponding to data “01”) and the fourth state (corresponding to data “00”) among the three reference current levels. The resource J82 is for obtaining a reference current level “L” which is between the first state (FIG. 9A) (corresponding to data “11”) and the second state (corresponding to data “10”).
Then, in the second sensing period, the sensing operation is performed in substantially the same manner as in the first sensing period, and the second data latch circuit J5 latches the output from the sense amplifier J3 in the second sensing period.
In this manner, the 2-bit data stored in the selected cell J7 can be read.
The above description is regarding quaternary memory cells which can store 2-bit data in one memory cell. The time division sensing system can also be used for memory cells which can store n-bit data in one memory cell. In this case, the n-bit data can be read by performing the sensing operation as few as n times.
With the time division sensing system, a plurality of bits of data can be read using as few as one sense amplifier. Therefore, the area of the chip occupied by the sense amplifier, the level of current instantaneously consumed, and the like can be minimized. Since the circuit constants of the current load circuits J1 and J2 and other parameters are switched, a larger operation margin can be easily obtained for each cycle of sensing operation.
However, the time division sensing system requires a setup/hold time for latching the output from the sense amplifier J3 by the data latch circuits J4 and J5 for each cycle of sensing operation, and also requires a switching time between the sensing periods. Therefore, data read cannot be easily performed at high speed.
Next, the parallel sensing system by which the cell current level is compared with a plurality of reference current levels at a time will be described.
As an example of the parallel sensing system, an operation of reading data from multi-level memory cells which can store 2-bit data in one memory cell (FIG. 9A) will be described with reference to FIG. 11.
FIG. 11 is a circuit diagram of a conventional reading circuit H100 for reading data from memory cells in the parallel sensing system.
In FIG. 11, the reading circuit H100 reads data from only one memory cell. This is merely exemplary, and the reading circuit H100 may read data from one selected memory cell among a plurality of memory cells.
The reading circuit H100 includes a current load circuit H1 for applying a voltage to a drain of a selected cell H8 from which data is to be read, so as to obtain a reading current (cell current), and current load circuits H2 through H4 for applying voltages to the resources H80 through H82 of the reference current so as to obtain reference current levels respectively. The current load circuits H1 through H4 have the same characteristics.
A sensing line H9 is provided for connecting the drain of the selected cell H8 to the current load circuit H1, and a reference line H10 is provided for connecting the resource H80 to the current load circuit H2. A reference line H11 is provided for connecting the resource H81 to the current load circuit H3, and a reference line H12 is provided for connecting the resource H82 to the current load circuit H4.
The sensing line H9 and the reference line H10 are respectively connected to input sections of a sense amplifier H5. The sense amplifier H5 senses the potential difference between the potential of the sensing line H9 and the potential of the reference line H10 and amplifies the potential difference.
The sensing line H9 and the reference line H11 are respectively connected to input sections of a sense amplifier H6. The sense amplifier H6 senses the potential difference between the potential of the sensing line H9 and the potential of the reference line H11 and amplifies the potential difference.
The sensing line H9 and the reference line H12 are respectively connected to input sections of a sense amplifier H7. The sense amplifier H7 senses the potential difference between the potential of the sensing line H9 and the potential of the reference line H12 and amplifies the potential difference.
A logic circuit H13 is connected to an output section of each of the sense amplifiers H5 through H7, and 2-bit data is read from an output section of the logic circuit H13 via lines H14 and H15.
The reading circuit H100 of the parallel sensing system having the above-described structure reads data from the selected cell H8 in the following manner.
First, an appropriate voltage is applied to a gate and a drain of the selected cell H8, thereby generating a cell current flowing through the selected cell H8. Next, the potential of the sensing line H9 is dropped in accordance with the generated cell current.
Similarly, a reference current is generated flowing from the resource H80. In accordance with the reference current, the potential of the reference line H10 is dropped. When a reference current is generated flowing from the resource H81, the potential of the reference line H11 is dropped in accordance with the generated reference current. When a reference current is generated flowing from the resource H82, the potential of the reference line H12 is dropped in accordance with the generated reference current.
The resource H80 of the reference current is for obtaining a reference current level “H” which is between the third state (FIG. 9A) (corresponding to data “01”) and the fourth state (corresponding to data “00”) among the three reference current levels. The resource H81 of the reference current is for obtaining a reference current level “M” which is between the second state (FIG. 9A) (corresponding to data “10”) and the third state (corresponding to data “01”). The resource H82 of the reference current is for obtaining a reference current level “L” which is between the first state (FIG. 9A) (corresponding to data “11”) and the second state (corresponding to data “10”).
In general, as the resources H80 through H82, reference cells having the same structure and the same characteristics as those of the memory cell, whose threshold voltages are tightly adjusted, are used in order to obtain appropriate reference currents.
The potential difference between the potential of the sensing line H9 and the potential of each of the reference lines H10 through H12 is sensed in parallel and amplified by each of the sense amplifiers H5 through H7. Thus, 3-bit data is output from the sense amplifiers H5 through H7 to the logic circuit H13.
The 3-bit data output from the sense amplifiers H5 through H7 is converted by the logic circuit H13 into 2-bit data, which is the data actually read.
With reference to FIGS. 12 and 13, a specific embodiment of the logic circuit H13 (FIG. 11) will be described.
FIG. 12 shows the relationship between the cell current level which the memory cell can have and the reference current level, and the outputs from the sense amplifiers H5 through H7 (FIG. 11).
As described above, the reference current level from the resource H80 is set to be level “H” between the third state (corresponding to data “01”) and the fourth state (corresponding to data “00”). The reference current level from the resource H81 is set to be level “M” between the second state (corresponding to data “10”) and the third state (corresponding to data “01”). The reference current level from the resource H82 is set to be level “L” between the first state (corresponding to data “11”) and the second state (corresponding to data “10”).
In this example, when the cell current level is higher than the reference current level, the sense amplifiers H5 through H7 each output data “1” to the logic circuit H13. When the cell current level is lower than the reference current level, the sense amplifiers H5 through H7 each output data “0” to the logic circuit H13.
As shown in FIG. 12, the output from the sense amplifier H5 is “1” when the cell current level is in one of the first through third states, and is “0” when the cell current level is in the fourth state. The output from the sense amplifier H6 is “1” when the cell current level is in one of the first and second states, and is “0” when the cell current level is one of the third and fourth states. The output from the sense amplifier H7 is “1” when the cell current level is in the first state, and is “0” when the cell current level is one of the second through fourth states.
FIG. 13 shows a truth table for explaining the conversion of the 3-bit input into 2-bit output performed by the logic circuit H13 (FIG. 11). The logic circuit H13 is a 3-bit input/2-bit output logic circuit, which realizes the truth table shown in FIG. 13.
As shown in FIG. 13, when the outputs of the sense amplifiers H5, H6 and H7 are “0”, “0” and “0”, this means that the cell current level is in the fourth state corresponding to data “00”. In this case, the logic circuit H13 outputs “0” via the line H14 and outputs “0” via the line H15.
When the outputs of the sense amplifiers H5, H6 and H7 are “1”, “0” and “0”, this means that the cell current level is in the third state corresponding to data “01”. In this case, the logic circuit H13 outputs “0” via the line H14 and outputs “1” via the line H15.
When the outputs of the sense amplifiers H5, H6 and H7 are “1”, “1” and “0”, this means that the cell current level is in the second state corresponding to data “10”. In this case, the logic circuit H13 outputs “1” via the line H14 and outputs “0” via the line H15.
When the outputs of the sense amplifiers H5, H6 and H7 are “1”, “1” and “1”, this means that the cell current level is in the first state corresponding to data “11”. In this case, the logic circuit H13 outputs “1” via the line H14 and outputs “1” via the line H15.
The reading circuit H100 for reading data from quaternary memory cells which can store 2-bit data in one memory cell includes three sense amplifiers. A reading circuit for reading data from multi-level memory cells which can store n-bit data in one memory cell theoretically needs to include 2n−1 sense amplifiers.
With the parallel sensing system, n-bit data can be read in one cycle of sensing operation by allowing a plurality of sense amplifiers (H5 through H7 in the example of FIG. 11) to operate in parallel. Accordingly, the parallel sensing system is very advantageous for increasing the speed of data read.
However, the parallel sensing system, which requires a plurality of sense amplifiers, is disadvantageous in, for example, increasing the area of the chip occupied by sense amplifiers and in increasing the level of current instantaneously consumed.
The current load circuits H1 through H4 have the same characteristics but the sense amplifiers H5 through H7 have different operating points since the sense amplifiers H5 through H7 receive different levels of reference current. Therefore, in the case of the reading circuit H100, it is necessary to obtain a uniform operation margin over a wide range of the cell current levels including the operating points of the sense amplifiers H5 through H7. This makes it difficult to enlarge the absolute operation margin at each of the operating points of the sense amplifiers H5 through H7.
Hereinafter, the operation margin of the reading circuit in the time division sensing system and the parallel sensing system will be described. In the following description, the term “sensing voltage conversion efficiency” is defined as the absolute value of the sensing voltage difference/cell current difference, which is the ratio of the sensing voltage difference with respect to the cell current difference. The sensing voltage difference represents the difference between the sensing voltage and the reference voltage. The cell current difference represents the difference between the cell current level and the reference current level. The sensing voltage represents the potential of the sensing line, and the reference voltage represents the potential of the reference line. As the sensing voltage conversion efficiency is larger, the operation margin of the reading circuit is larger. Even when the cell current difference is the same, a larger sensing voltage difference (i.e., a higher sensing voltage conversion efficiency) leads to a larger operation margin. A larger operation margin is more advantageous for shortening the reading time.
The operation margin and the sensing voltage conversion efficiency will be described by showing the relationship between the cell current and the sensing voltage in accordance with the load characteristics of the current load circuits.
FIG. 14A shows a reading circuit 200 using a resistance as a general current load.
In the reading circuit 200 shown in FIG. 14A, a current load circuit L10 uses a resistance L1 as a current load, and a current load circuit L20 uses a resistance L2 as a current load.
When a cell current flowing through a memory cell L5 is generated, the potential of a sensing line L3 is dropped in accordance with the level of the generated cell current.
Similarly, when a reference current flowing through a reference cell L6 is generated, the potential of a reference line L4 is dropped in accordance with the level of the generated reference current.
FIG. 14B is a graph illustrating the relationship between the cell current and the sensing voltage in the reading circuit 200. In FIG. 14B, the absolute value of the gradient of the curve represents the sensing voltage conversion efficiency.
Since the resistances L1 and L2 are used as the current loads of the current load circuits L10 and L20 of the reading circuit 200, the curve representing the relationship between the sensing voltage and the cell current is linear.
In the reading circuit 200 having a linear load characteristic, the sensing voltage conversion efficiency is uniform (constant) over the entire region of the cell current levels.
In the parallel sensing system, the sensing operation needs to be performed at a plurality of operating points. Therefore, it is preferable to use a reading circuit having a linear load characteristic as shown in FIG. 14B in order to obtain a uniform operation margin at each of the operating points. However, such a reading circuit has a lower sensing voltage conversion efficiency than that of a reading circuit having a nonlinear load characteristic (described below) and thus is not suitable for multi-level memory cells having a smaller difference in the cell current level.
In the case where the number of operating points used in one cycle of sensing operation is limited as in the time division sensing system, a reading circuit having a nonlinear load characteristic, by which the sensing voltage conversion efficiency in the vicinity of the operating point is higher than the rest, can be used.
FIG. 15A shows a reading circuit 300 as an example of a current load circuit having a nonlinear load characteristic. In the reading circuit 300, PMOS transistors are current-mirror-connected to each other.
In the reading circuit 300 shown in FIG. 15A, a current load circuit K10 uses a PMOS transistor K1 as a current load, and a current load circuit K20 uses a PMOS transistor K2 as a current load. A drain and a gate of the PMOS transistor K2 are connected to each other, and a gate of the PMOS transistor K1 is connected to a gate of the PMOS transistor K2 via a reference line K4.
When a cell current flowing through a reference cell K6 is generated, the potential of a reference line K4 is dropped in accordance with the level of the generated reference current. Similarly, when a cell current flowing through a memory cell K5 is generated, the potential of a sensing line K3 is dropped in accordance with the level of the generated cell current.
FIG. 15B is a graph illustrating the relationship between the cell current and the sensing voltage in the reading circuit 300.
Since the PMOS transistors K1 and K2 are used as the current loads of the current load circuits K10 and K20, the curve representing the relationship between the sensing voltage and the cell current is nonlinear.
In the reading circuit 300 having a nonlinear load characteristic, the sensing voltage conversion efficiency (represented by the absolute value of the gradient of the curve in FIG. 15B) can be higher in the vicinity of the point at which the cell current level is equal to the reference current level than that in the reading circuit 200 (FIGS. 14A and 14B). When the sensing voltage conversion efficiency is higher, the reading operation margin can be larger even when the cell current difference is small. Therefore, such a reading circuit is suitable for multi-level memory cells. However, such a reading circuit has a lower sensing voltage conversion efficiency in the region of the cell current levels other than the reference current level, and thus it is not easy to perform the sensing operation at a plurality of operating points.
As described above, when the time division sensing system is used for multi-level memory cells adopting a current sensing system, it is preferable to use a reading circuit having a nonlinear reading load characteristic in order to enlarge the operation margin in the region around the operating point. However, this requires a setup/hold time for latching the output from the sense amplifier for each sensing period, and it is not easy to increase the reading time.
When the parallel sensing system is used, it is necessary to enlarge substantially uniform operation margins at each of a plurality of operating points. Thus, it is difficult to enlarge an absolute operation margin. Accordingly, the parallel sensing system is not suitable for multi-level memory cells.